1. Field of the Invention
The present disclosure relates to a thin-film transistor (“TFT”, hereinafter) array substrate, more specifically to a method of manufacturing an LTPS array substrate.
2. Description of the Related Art
Liquid Crystal Display (LCD) or Active Matrix/Organic Light Emitting Diode (AMOLED) displays images by the light transmittance of liquid crystal (LC) controlled by electric field, or by the lightness of the organic luminescent materials controlled by electric current. To these displays, it is necessary to utilize TFT array substrate to drive and control the pixels by voltage or current. The TFT array substrate comprises scanning lines, signal lines and TFT. In order to achieve the requirement of high resolution, the current TFT array substrate is mostly manufactured by the low-temperature polysilicon (LTPS) manufacturing process. As the TFT array substrate, especially the LTPS substrate is manufactured by the semiconductor process and a plurality of photomask processes, which are very complex. Consequently, the cost is relatively high.
A relatively whole photomask process includes a plurality of processes, such as the cleaning process, the thin-film deposition process, the photoetch process, the etching processes, the photoresist stripping and the examining process. Moreover, some processes using the photomask further comprise the process of laser annealing and ions implantation. Presently, the mass-produced LTPS array substrates are usually made by the CMOS process including 9 or 8 photomasks.
FIG. 1 shows a simplified diagram of the CMOS process including 9 photomasks, successively including: 1: P—Si Pattern Process, by which a polysilicon is formed after dry etching, and FIG. 2a shows a diagram of using the photomask in this step; 2: Channel Doping Process, by which the photomask used is shown by the sectional view in FIG. 2b; 3: N+Doping (S/D) Process, by which the P-type area is screened and the N-type area is implanted with ions (source/drain); 4: Gate Electrode Deposition (M1) Process, by which a first metal layer is formed and the gate is defined; 5: P+Doping Process, by which the N-type area is screened and the P-type area is implanted with ions; 6: Contact Hole Process, by which contact holes are formed; 7: Wiring Layer (M2) Process, by which the wiring layer is formed after forming a second metal layer and defining the pattern of date lines; 8: PLN (Planarization) Process, by which a planar layer is deposited and contact holes are formed; 9: Pixel Electrode Process, by which the shape of pixel electrode is defined.
FIG. 3 shows a simplified diagram of the CMOS process including 8 photomasks. Actually, the essence thereof is to cancel the second step in the process including 9 photomasks shown in FIG. 1, i.e., the Channel Doping Process is not performed. However, there are defects in the CMOS process including 8 photomasks in the flowing three aspects.
The redundancy of the design is smaller. The redundancy becomes smaller from 2.64V to 1.64V as FIGS. 4a and 4b show, wherein, Vcom ranges form 0.64V to 4.44V, whose voltage difference is 3.8V; data-signal ranges form 0.94V to 4.14V, when the coupling occurs, the data signal is changed by the following formula: 0.94−3.8=−2.86V; VgateH: 8.5−4.14=4.36V (VGS@gate ON); VgateL: −4−(−2.86)=−1.14V (VGS@gate OFF).
The power loss is higher. As Channel Doping Process is canceled, the migration rate will be reduced. In order to acquire the same output current, it is necessary to increase the driving voltage of the panel, which causes a higher power consumption of the panel.
The requirement of the uniformity for Vthn and Vthp is higher. As the migration rate is reduced, it is necessary to reduce the channel length of the devices to increase W/L in design, which needs short channel devices of excellent uniformity. Hence, a p-Si film with better uniformity is necessary to be used, which increases the difficulty of the process and design.
A related art has disclosed a method for manufacturing a TFT substrate in which a channel length can be stably formed while the number of masks is reduced, and a method for manufacturing a TFT substrate which can individually control impurity concentrations for channels of an n-type TFT and a p-type TFT without increasing the number of masks. A method for manufacturing a TFT substrate includes processing a gate of the n-type TFT, a gate of the p-type TFT, and an upper capacitor electrode by using a half-tone mask instead of some of normal masks to reduce the number of masks, and changing impurity concentrations of semiconductor films located in regions which become a channel of the n-type TFT, a source and a drain of the n-type TFT, a channel of the p-type TFT, a source and a drain of the p-type TFT, and an lower capacitor electrode, by using a pattern of the half-tone mask and a normal mask.
Another related art has disclosed an LTPS-LCD structure and a method for manufacturing the structure are provided. The structure comprises a substrate where a plurality of pixels are formed thereon. Each of these pixels comprises a control area, a capacitance area, and a display area. The structure is initially formed with a transparent electrode on the substrate, followed by a control device, a capacitance storage device. The display unit is then formed on the control area, the capacitance area, and the display area, respectively. As a result, the capacitance of the structure can be enhanced and the manufacturing processes of masks can be reduced. Consequently, it did not solve the problem that the cost of manufacturing the TFT array substrate is relatively high.